The company isn’t giving Intel a chance to catch up either, and now they’re targeting NVIDIA as well.
Since the introduction of the EPYC product line, AMD’s presence in the server market has been a major success story since the launch of Rome and later the Milan platform. To keep it that way, the company has shown how they are preparing for the next period.
A third-generation EPYC fleet equipped with 3D V-Cache technology, from 16 to 64 cores, is expected to arrive inside the Milan platform from a processor. A common feature of all of them is that they offer 768 MB of L3 cache instead of the previous 256 MB maximum, while the parameters of the L1 and L2 caches do not change. In terms of caching, the company calculates the capacity of L2 and L3 together, so the value on the slide, up to 804 MB, comes out, but that’s really just a matter of interpretation.
The extra cache makes the most sense if the task performed is data-intensive, such as finite element analysis, structural analysis, computer flow engineering, and possibly design automation. In such an environment, the current launch of the Milan platform already had an advantage over the competition, but the scissors only opened up even more with the new variant. According to AMD’s measurements, an EPYC with a 16-core 3D V-Cache design is roughly 66% faster than its 16-core counterpart without 3D V-Cache during RTL verification, a significant difference. And it would be difficult to bring this advantage differently, because the typical problem of the workflow itself is that the limitation is mostly the powerful data processing, that is, it is possible to capture more cores, but it is nowhere near as small as half a gigabyte extra. with cache. It is also very important that these benefits only come by themselves, ie it is not necessary to change the written code, although the possibility of further optimization is open.
There are a number of environments in the server market where 3D V-Cache offers an average 50% advantage, and in these environments it will be very difficult to fight the cached heavily packed EPYC CPUs that will be available for purchase in the first quarter of next year. Because AMD does not use a new enclosure, the BIOS update will be able to apply the latest enhancements to existing servers.
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